Digital Delay Units seERiES DDU-12 10 Taps ECL Interfaced Test Conditions: B Input pulse-width: 150% of total delay. @ Input pulse rise-time: <6 ns Features: @ Input pulse voltage: .7V w Input & Output ECL Buffered a fooaingadee from 20% to 80% of @ 10 Equally Spaced Taps @ Delay time measured at 50% of leading edge. m PC Board Economy Achieved @ All measurements taken @ Vie = 5.2V and . . Ta= 25C Specifications: m Unless otherwise specified, all time-delays are referenced to the input pin. @ Total Delay Tolerance: +5% or better, or 2 NS whichever is greater. w No. Taps: 10 equally spaced w@ Rise-Time: 2 ns typical w Logic 1 input voltage: .96V @ Logic 1 input current: .52MA m@ Logic 0 input voltage: 1.65 V @ Logic 0 input current: 1.04uA = Supply Voltage: 5.2V m@ Operating Temperature: 30C to 85C m@ Power Dissipation: 400 MW typ. (no load) m= Temperature Coefficient: 100 PPM/C Part No. *DDU-12-10 % DDU-12-20 % DDU-12-25 # DDU-12-40 % DDU-12-50 DDU-12-75 DDU-12-100 DDU-12-150 DDU-12-200 DDU-12-250 DDU-12-300 DDU-12-400 DDU-12-500 DDU-12-750 DDU-12-1000 DDU-12-1500 % Time delay measurements referenced to DATA DELAY DEVICES Inc. @ 385 Lakeview Avenue, Clifton, New Jersey 07011 @ (201) 772-1106 # TWX 710-989-7008 15